1. Field of the Invention
Apparatuses consistent with the present invention relate to a radio frequency (RF) transmitter, and more particularly, to a power amplifier circuit which can effectively amplify a power by classifying an envelope of an input high frequency signal that corresponds to a high level and a low level, and controlling a voltage to be supplied to a power amplification end.
2. Description of Related Art
In a transmitter of a system for high speed wireless communication such as a mobile phone, a digital multimedia broadcasting (DMB) phone, a personal digital assistant (PDA), and the like, various transmission schemes including an envelope modulation, for example, a quadrature phase shift keying (QPSK) modulation, a quadrature amplitude modulation (QAM), and the like, have been adopted. For the transmitter, a power amplifier is utilized to amplify a high frequency signal containing certain information. An output of the power amplifier is transmitted to a correspondent system via an antenna.
FIG. 1 illustrates a structure of a related art power amplifier 100. Referring to FIG. 1, the power amplifier 100 includes a power voltage control circuit 110 and an amplification stage 120.
Generally, an input signal PIN is a carrier signal in a high frequency domain for high speed wireless communication. The input signal PIN is amplified by the amplification stage 120. The amplification stage 120 amplifies the input signal PIN using amplifiers in various stages. In this instance, an operating voltage level of the signal, amplified by the amplification stage 120, is controlled by the power voltage control circuit 110, and an output signal POUT is generated according to the controlled signal. The power voltage control circuit 110 receives an envelope signal VRAMP for specifying a voltage level of the output signal POUT, to control the operating voltage level of the amplified signal by the amplification stage 120.
The power voltage control circuit 110 amplifies the envelope signal VRAMP, having an envelope which is determined by modulation scheme, for example, QPSK modulation, QAM modulation, and the like, or eliminates a noise component which is introduced into the envelope signal VRAMP. Accordingly, the operating voltage level of the power amplifier 110 varies by the power voltage control circuit 100 according to the envelope size of the high frequency signal, and the output signal POUT of the high frequency signal is transmitted via an antenna.
A transistor is generally inserted to an end of the power voltage control circuit 110. Specifically, the output signal POUT is generated by mixing a transistor output at the end of the power voltage control circuit 110 with the amplified signal by the amplification stage 120. As described above, since an active device, such as the transistor, is utilized at the end of the power voltage control circuit 110 for signal mixing, a comparatively great amount of power loss and signal distortion occurs. Specifically, as shown in FIG. 2, when the signal distortion does not exist, i.e., in a normal state, the output signal POUT may be output in an envelope form shaped in a waveform 210. However, like a waveform 220, the output signal POUT is distorted in ranges where a signal level is greater than a predetermined level and less than the predetermined level due to non-linearity of the active device. Also, since the active device has a comparatively greater resistance than a passive device, power consumption is greater than the passive device.
Also, as shown in FIG. 3, a transistor Q1 is generally provided at an end of the amplification stage 120. A metal-oxide semiconductor field effect transistor (MOSFET), a heterojunction bipolar transistor (HBT), a bipolar junction transistor (BJT), and the like, may be utilized for the transistor Q1. The transistor Q1 in the form of an N-channel MOSFET receives an output signal of an amplifier in a previous stage, as an input signal. As shown in FIG. 4, the transistor Q1 shows an Ids-Vds characteristics according to a gate bias voltage VGS and a drain voltage VDS corresponding to an operating point voltage. Here, Vds corresponds to a voltage between a drain and a source of the transistor Q1, and Ids corresponds to a current between the drain and the source. As an example, the transistor Q1 operates on a load line 412 by considering available headroom. Specifically, the transistor Q1 operates on the load line 412 to be capable of covering the output signal POUT with a greater envelope level as shown in a waveform 420. However, when the output signal POUT has a small envelope level like a waveform 410, the transistor Q1 operates on a load line 411. Accordingly, a corresponding load line may be reduced by temporarily decreasing a drain voltage of the transistor Q1 in proportion to an envelope level with respect to the output signal POUT with the small envelope level like the waveform 410. As shown in FIG. 4, since the transistor Q1 generally operates around an operating point PP, a power loss increases.